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ADT7473
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA, and
the transaction ends.
The single byte write operation is illustrated in Figure 21.
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the
following events occur:
? SMBALERT is pulled low.
? The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general
call address that must not be used as a specific device
address.
? The device whose SMBALERT output is low responds
to the alert response address, and the master reads its
device address. The address of the device is now known
and can be interrogated in the usual way.
? If more than one device’s SMBALERT output is low,
the one with the lowest device address has priority in
1
2
3
4
5
6
7
8
accordance with normal SMBus arbitration.
S ADDRESS W A
SLAVE
REGISTER
ADDRESS
A
DATA A P
Once the ADT7473/ADT7473 ? 1 has responded to the
alert response address, the master must read the status
Figure 21. Single-byte Write to a Register
Read Operations
The ADT7473/ADT7473 ? 1 uses the following SMBus
read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been previously set
up. In this operation, the master device receives a single byte
from a slave device, as follows:
1. The master device asserts a start condition on
SDA.
registers, and the SMBALERT is cleared only if the error
condition is gone.
SMBus Timeout
The ADT7473/ADT7473 ? 1 includes an SMBus timeout
feature. If there is no SMBus activity for 35 ms, the
ADT7473/ADT7473 ? 1 assumes the bus is locked and
releases the bus. This prevents the device from locking or
holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so
it can be disabled.
Table 8. CONFIGURATION REGISTER 1 (REG. 0X40)
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
Bit
<6> TODIS
Description
0: SMBus Timeout Enabled (Default)
1: SMBus Timeout Disabled
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
In the ADT7473/ADT7473 ? 1, the receive byte protocol
is used to read a single byte of data from a register whose
address has previously been set by a send byte or write byte
operation. This operation is illustrated in Figure 22.
Voltage Measurement Input
The ADT7473/ADT7473 ? 1 has one external voltage
measurement channel and can also measure its own supply
voltage, V CC . Pin 14 can measure V CCP . The V CC supply
voltage measurement is carried out through the V CC pin
(Pin 3). The V CCP input can be used to monitor a chipset
supply voltage in computer systems.
S ADDRESS R A
1 2 3
SLAVE
4
DATA
5 6
A P
Analog-to-Digital Converter
All analog inputs are multiplexed into the on-chip,
successive approximation, analog-to-digital converter.
(ADC) This has a resolution of 10 bits. The basic input range
Figure 22. Single-byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
is 0 V to 2.25 V, but the input has built-in attenuators to
allow measurement of V CCP without any external
components. To allow for the tolerance of the supply
voltage, the ADC produces an output of 3/4 full scale
(768 decimal or 300 hexadecimal) for the nominal input
voltage and thus has adequate headroom to deal with
overvoltages.
output or an SMBALERT. One or more outputs can be
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